2025 · Conference paper
CORD: Low-Latency, Bandwidth-Efficient and Scalable Release Consistency via Directory Ordering
ACM ISCA, 2025
Distinguished Artifact Award, IEEE Micro’s Top Picks in Computer Architecture 2025
Abstract
Multi-processing-unit systems increasingly use cache-coherent shared memory and write-through accesses for producer-consumer communication. Existing release-consistency protocols order these writes at the source processor, causing unnecessary communication with the last-level-cache directory. CORD instead orders write-through accesses directly at the directory and uses new mechanisms to minimize ordering metadata across multiple directories. Gem5 evaluations show a 24 percent average performance improvement and 13 percent traffic reduction over source ordering with less than 1 percent storage, area, and power overhead. Compared with hand-optimized message passing, CORD incurs only about 3 percent performance overhead with a much simpler programming model.
Publication details
- Venue
- ACM ISCA
- Publication year
- 2025
- Awards
- Distinguished Artifact Award, IEEE Micro’s Top Picks in Computer Architecture 2025
BibTeX
@inproceedings{cord,
author = {Yu, Yanpeng and Oswald, Nicolai and Khandelwal, Anurag},
title = {{CORD: Low-Latency, Bandwidth-Efficient and Scalable Release Consistency via Directory Ordering}},
year = {2025},
month = jun,
booktitle = {ACM ISCA},
award = {Distinguished Artifact Award, IEEE Micro's Top Picks in Computer Architecture 2025}
}